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src/soc: Get rid of whitespace before tab

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Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-05-28 16:26:43 +02:00 • committed by Patrick Georgi
commit 05498a254d
29 changed files with 104 additions and 104 deletions
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2
src/soc/nvidia/tegra/types.h
View file

@ -18,7 +18,7 @@
#define EFAULT 1
#define EINVAL 2
#define ETIMEDOUT 3
#define ETIMEDOUT 3
#define ENOSPC 4
#define ENOSYS 5
#define EPTR 6

2
src/soc/nvidia/tegra124/display.c
View file

@ -216,7 +216,7 @@ void display_startup(struct device *dev)
{
struct soc_nvidia_tegra124_config *config = dev->chip_info;
struct display_controller *disp_ctrl = (void *)config->display_controller;
struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
struct tegra_dc *dc = &dc_data;
u32 plld_rate;

12
src/soc/nvidia/tegra124/include/soc/clk_rst.h
View file

@ -471,12 +471,12 @@ enum {
#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define HCLK_DISABLE (1 << 7)
#define HCLK_DIVISOR_SHIFT 4
#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define PCLK_DISABLE (1 << 3)
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define HCLK_DISABLE (1 << 7)
#define HCLK_DIVISOR_SHIFT 4
#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define PCLK_DISABLE (1 << 3)
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)

4
src/soc/nvidia/tegra124/sor.c
View file

@ -606,8 +606,8 @@ static void dump_sor_reg(struct tegra_dc_sor_data *sor)
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
int is_lvds)
{
const struct tegra_dc *dc = sor->dc;
const struct tegra_dc_dp_data *dp = dc->out;
const struct tegra_dc *dc = sor->dc;
const struct tegra_dc_dp_data *dp = dc->out;
const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg;
const struct soc_nvidia_tegra124_config *config = dc->config;

14
src/soc/nvidia/tegra210/include/soc/clk_rst.h
View file

@ -416,7 +416,7 @@ enum {
#define PLLM_MISC2_KCP_SHIFT 1
#define PLLM_MISC2_KVCO_SHIFT 0
#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
#define PLLM_EN_LCKDET (1 << 4)
#define PLLM_EN_LCKDET (1 << 4)
/* PLLU specific registers */
#define PLLU_MISC_IDDQ (1U << 31)
@ -527,12 +527,12 @@ enum {
#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define HCLK_DISABLE (1 << 7)
#define HCLK_DIVISOR_SHIFT 4
#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define PCLK_DISABLE (1 << 3)
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define HCLK_DISABLE (1 << 7)
#define HCLK_DIVISOR_SHIFT 4
#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define PCLK_DISABLE (1 << 3)
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
/* CPU_SOFTRST_CTRL2_0 0x388 */
#define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff

2
src/soc/nvidia/tegra210/include/soc/tegra_dsi.h
View file

@ -149,7 +149,7 @@
#define PKT_LP (1 << 30)
#define NUM_PKT_SEQ 12
#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20)
#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20)
#define DSIB_MODE_SHIFT 1
#define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT)
#define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT)