From 05246a59342ac21027ddce017401f73adeac7c43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= Date: Sat, 14 Mar 2026 14:09:59 +0100 Subject: [PATCH] mb/asus: Add Maximus VII Impact (Haswell/Broadwell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on Autoport with subsequent manual tweaking. The system boots with an Intel i7-4770K using Haswell NRI. Thanks to Angel Pons for fixing S3 suspend/resume. Working: - Haswell CPUs - Haswell NRI - Both DDR3 DIMM slots - HDMI Port - DP Port - All rear USB ports - Audio Jack - Ethernet port - WiFi and M.2 - All SATA ports - Discrete Graphics (tested with AMD R9 Nano) - TPM 2.0 - S3 suspend and resume Not working: - Rear double-digit display does not show CPU temp. - Known issue: Broadwell (non-ULT) CPUs are not yet supported in coreboot Not (yet) tested: - USB headers Change-Id: I6813adce267af6bd449f72b0595dfec9277961bf Signed-off-by: Jan Philipp Groß Reviewed-on: https://review.coreboot.org/c/coreboot/+/91672 Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/asus/maximus_vii_impact/Kconfig | 29 +++ .../asus/maximus_vii_impact/Kconfig.name | 4 + .../asus/maximus_vii_impact/Makefile.mk | 5 + .../asus/maximus_vii_impact/acpi/ec.asl | 3 + .../asus/maximus_vii_impact/acpi/platform.asl | 10 + .../asus/maximus_vii_impact/acpi/superio.asl | 3 + .../asus/maximus_vii_impact/board_info.txt | 7 + .../asus/maximus_vii_impact/data.vbt | Bin 0 -> 6144 bytes .../asus/maximus_vii_impact/devicetree.cb | 134 +++++++++++ .../asus/maximus_vii_impact/dsdt.asl | 27 +++ .../asus/maximus_vii_impact/gma-mainboard.ads | 21 ++ src/mainboard/asus/maximus_vii_impact/gpio.c | 211 ++++++++++++++++++ .../asus/maximus_vii_impact/hda_verb.c | 33 +++ .../asus/maximus_vii_impact/romstage.c | 37 +++ 14 files changed, 524 insertions(+) create mode 100644 src/mainboard/asus/maximus_vii_impact/Kconfig create mode 100644 src/mainboard/asus/maximus_vii_impact/Kconfig.name create mode 100644 src/mainboard/asus/maximus_vii_impact/Makefile.mk create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/ec.asl create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/platform.asl create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/superio.asl create mode 100644 src/mainboard/asus/maximus_vii_impact/board_info.txt create mode 100644 src/mainboard/asus/maximus_vii_impact/data.vbt create mode 100644 src/mainboard/asus/maximus_vii_impact/devicetree.cb create mode 100644 src/mainboard/asus/maximus_vii_impact/dsdt.asl create mode 100644 src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads create mode 100644 src/mainboard/asus/maximus_vii_impact/gpio.c create mode 100644 src/mainboard/asus/maximus_vii_impact/hda_verb.c create mode 100644 src/mainboard/asus/maximus_vii_impact/romstage.c diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig b/src/mainboard/asus/maximus_vii_impact/Kconfig new file mode 100644 index 0000000000..1e8be71e2f --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VII_IMPACT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asus/maximus_vii_impact" + +config MAINBOARD_PART_NUMBER + default "Maximus VII IMPACT" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig.name b/src/mainboard/asus/maximus_vii_impact/Kconfig.name new file mode 100644 index 0000000000..d5a59d8f4c --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VII_IMPACT + bool "Maximus VII IMPACT" diff --git a/src/mainboard/asus/maximus_vii_impact/Makefile.mk b/src/mainboard/asus/maximus_vii_impact/Makefile.mk new file mode 100644 index 0000000000..c9500cfe9b --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_impact/board_info.txt b/src/mainboard/asus/maximus_vii_impact/board_info.txt new file mode 100644 index 0000000000..2913218dfe --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://rog.asus.com/motherboards/rog-maximus/rog-maximus-vi-impact-model/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2014 diff --git a/src/mainboard/asus/maximus_vii_impact/data.vbt b/src/mainboard/asus/maximus_vii_impact/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..04c363ae3fd45ed0952e76eab914af8ea675966f GIT binary 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b/src/mainboard/asus/maximus_vii_impact/devicetree.cb @@ -0,0 +1,134 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + register "usb_xhci_on_resume" = "false" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x003c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002246" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x85c4 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8603 + end + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: mPCIe WiFi + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf1 = 0xb3 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xd0 + end + device pnp 2e.109 on # GPIO3 + irq 0xe5 = 0x10 + irq 0xe7 = 0x70 + end + device pnp 2e.209 on # GPIO4 + irq 0xf1 = 0x36 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xef + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0x01 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vii_impact/dsdt.asl b/src/mainboard/asus/maximus_vii_impact/dsdt.asl new file mode 100644 index 0000000000..2eb0805cf2 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads new file mode 100644 index 0000000000..938687fac9 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vii_impact/gpio.c b/src/mainboard/asus/maximus_vii_impact/gpio.c new file mode 100644 index 0000000000..7b4720c012 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vii_impact/hda_verb.c b/src/mainboard/asus/maximus_vii_impact/hda_verb.c new file mode 100644 index 0000000000..c310165c53 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc900_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438603), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x4007c000), + AZALIA_PIN_CFG(0, 0x18, 0x01a19050), + AZALIA_PIN_CFG(0, 0x19, 0x02a19060), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x01456140), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC900", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x10438603, + .address = 0, + .verbs = realtek_alc900_verbs, + .verb_count = ARRAY_SIZE(realtek_alc900_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vii_impact/romstage.c b/src/mainboard/asus/maximus_vii_impact/romstage.c new file mode 100644 index 0000000000..cb0a045d15 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};