From 04d52014262fbab22ca7d41193d7d7e00dc064bb Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Sun, 2 Nov 2025 23:11:22 +0100 Subject: [PATCH] treewide: Fix include guards Include guards should cover the whole file. Signed-off-by: Maximilian Brune Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871 Tested-by: build bot (Jenkins) Reviewed-by: Jakub "Kuba" Czapiga --- src/arch/riscv/include/arch/encoding.h | 17 +++++++++-------- src/include/console/cbmem_console.h | 3 ++- src/include/cpu/amd/amd64_save_state.h | 3 ++- src/mainboard/intel/harcuvar/hsio.h | 3 +-- src/soc/intel/meteorlake/include/soc/pci_devs.h | 4 ++-- .../intel/pantherlake/include/soc/pci_devs.h | 4 ++-- 6 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h index 6ab38bb9e7..28f89f87e8 100644 --- a/src/arch/riscv/include/arch/encoding.h +++ b/src/arch/riscv/include/arch/encoding.h @@ -214,13 +214,12 @@ #define rdcycle() read_csr(cycle) #define rdinstret() read_csr(instret) -#endif +#endif // __GNUC__ -#endif +#endif // __ASSEMBLER__ -#endif +#endif // __riscv -#endif /* Automatically generated by parse-opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H @@ -976,7 +975,7 @@ #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd #define CAUSE_STORE_PAGE_FAULT 0xf -#endif +#endif // RISCV_ENCODING_H #ifdef DECLARE_INSN DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) @@ -1240,7 +1239,7 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif +#endif // DECLARE_INSN #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) DECLARE_CSR(frm, CSR_FRM) @@ -1455,7 +1454,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif +#endif // DECLARE_CSR #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) @@ -1472,4 +1471,6 @@ DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -#endif +#endif // DECLARE_CAUSE + +#endif // RISCV_CSR_ENCODING_H diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 84a95dd593..12c3fb83bf 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -28,7 +28,8 @@ void cbmemc_copy_in(void *buffer, size_t size); void cbmem_dump_console_to_uart(void); void cbmem_dump_console(void); -#endif /* Retrieves the location of the CBMEM Console buffer in SMM mode */ void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out); + +#endif // _CONSOLE_CBMEM_CONSOLE_H_ diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h index 08b700afaa..fd0331d919 100644 --- a/src/include/cpu/amd/amd64_save_state.h +++ b/src/include/cpu/amd/amd64_save_state.h @@ -2,7 +2,6 @@ #ifndef __AMD64_SAVE_STATE_H__ #define __AMD64_SAVE_STATE_H__ -#endif #include #include @@ -111,3 +110,5 @@ typedef struct { u64 rcx; u64 rax; } __packed amd64_smm_state_save_area_t; + +#endif // __AMD64_SAVE_STATE_H__ diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index a79decd591..8986024472 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -606,5 +606,4 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_FIA_PCIE_ROOT_PORT_7)} } } }; #endif -#endif -/* _MAINBOARD_HSIO_H */ +#endif /* _MAINBOARD_HSIO_H */ diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index f52ca6edaa..0e55da24bb 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -222,8 +222,6 @@ #define PCI_DEV_GBE _PCI_DEV(ESPI, 6) #define PCI_DEV_NPK _PCI_DEV(ESPI, 7) -#endif - /* for common code */ #define MIN_PCH_SLOT PCI_DEV_SLOT_THC #define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE @@ -243,3 +241,5 @@ #define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 #define SA_DEV_IGD PCI_DEV_IGD #define SA_DEVFN_IGD PCI_DEVFN_IGD + +#endif // _SOC_METEORLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index 4d7d2301b0..25468ab39a 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -237,8 +237,6 @@ #define PCI_DEV_GBE _PCI_DEV(ESPI, 6) #define PCI_DEV_NPK _PCI_DEV(ESPI, 7) -#endif - /* for common code */ #define MIN_PCH_SLOT PCI_DEV_SLOT_THC #define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE @@ -258,3 +256,5 @@ #define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 #define SA_DEV_IGD PCI_DEV_IGD #define SA_DEVFN_IGD PCI_DEVFN_IGD + +#endif // _SOC_PANTHERLAKE_PCI_DEVS_H_