From 0464f1032aec2b74fb595fbfcd0c49090bf0e8cb Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 26 Feb 2026 09:38:05 -0800 Subject: [PATCH] soc/intel/common/feature/espi: Add common eSPI/LPC initialization This introduces a common implementation for eSPI/LPC initialization that handles generic IO decode range configuration and standard interrupt setup. This code is nearly identical across multiple Intel client platforms. The implementation includes: - soc_get_gen_io_dec_range(): Configures generic IO decode ranges from devicetree (gen1_dec through gen4_dec) - lpc_soc_init(): Performs legacy ISA/DMA initialization, enables CLKRUN for power gating, configures Serial IRQ mode, and sets up the interrupt controllers (IOAPIC, PIRQ, i8259) Platform-specific configuration is handled through the config_t typedef that each platform defines via its soc_chip.h header, eliminating the need for preprocessor conditionals. The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_ESPI Kconfig option and works across bootblock, romstage, and ramstage. Platforms that will use this common implementation: - Alder Lake - Meteor Lake - Panther Lake - Tiger Lake - Jasper Lake - Elkhart Lake Change-Id: Idbdecff1cef44dae90afb35ff6e2afca011ea5b4 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/91216 Reviewed-by: Huang, Cliff Reviewed-by: Guvendik, Bora Tested-by: build bot (Jenkins) --- src/soc/intel/common/feature/espi/Kconfig | 8 ++++ src/soc/intel/common/feature/espi/Makefile.mk | 5 ++ src/soc/intel/common/feature/espi/espi.c | 46 +++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 src/soc/intel/common/feature/espi/Kconfig create mode 100644 src/soc/intel/common/feature/espi/Makefile.mk create mode 100644 src/soc/intel/common/feature/espi/espi.c diff --git a/src/soc/intel/common/feature/espi/Kconfig b/src/soc/intel/common/feature/espi/Kconfig new file mode 100644 index 0000000000..521c7bbe5c --- /dev/null +++ b/src/soc/intel/common/feature/espi/Kconfig @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_FEATURE_ESPI + bool + help + Select this if the platform supports common eSPI/LPC initialization + with generic IO decode range configuration and standard interrupt + setup. This is applicable for most modern Intel client platforms. diff --git a/src/soc/intel/common/feature/espi/Makefile.mk b/src/soc/intel/common/feature/espi/Makefile.mk new file mode 100644 index 0000000000..69542218b3 --- /dev/null +++ b/src/soc/intel/common/feature/espi/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c diff --git a/src/soc/intel/common/feature/espi/espi.c b/src/soc/intel/common/feature/espi/espi.c new file mode 100644 index 0000000000..b0620c683d --- /dev/null +++ b/src/soc/intel/common/feature/espi/espi.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) +{ + const config_t *config = config_of_soc(); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); +}