diff --git a/src/mainboard/asus/tx97le/Config b/src/mainboard/asus/tx97le/Config new file mode 100644 index 0000000000..f1dbc549d0 --- /dev/null +++ b/src/mainboard/asus/tx97le/Config @@ -0,0 +1,42 @@ +arch i386 +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds +mainboardinit cpu/i386/reset16.inc +ldscript cpu/i386/reset16.lds + +option SERIAL_SUPERIO_BASEADDRESS=0x3f0 +option HAVE_PIRQ_TABLE=1 +mainboardinit superio/SMC/fdc37c67x/setup_serial.inc + +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc +northbridge intel/430tx +southbridge intel/piix4e +#mainboardinit cpu/p6/earlymtrr.inc +mainboardinit ram/dump_northbridge.inc +mainboardinit ram/ramtest.inc +mainboardinit mainboard/digitallogic/smartcore-p5/do_ramtest.inc + + +superio SMC/fdc37c67x + +#option ENABLE_FIXED_AND_VARIABLE_MTRRS +option PIIX4_DEVFN=0x38 +option NO_KEYBOARD=1 +option ZKERNEL_START=0xfffc0000 +option ZKERNEL_MASK=0x7f +option L430TX=1 +option SMC_BASE=0x3F0 +option CONFIG_UDELAY_TSC=1 + + +object mainboard.o +object irq_tables.o + +#cpu p6 +cpu p5 + +#option RAM_TEST=1 + diff --git a/src/mainboard/asus/tx97le/STATUS b/src/mainboard/asus/tx97le/STATUS new file mode 100644 index 0000000000..dfa4d7f5a6 --- /dev/null +++ b/src/mainboard/asus/tx97le/STATUS @@ -0,0 +1,27 @@ +# These are keyword-value pairs. +# a : separates the keyword from the value +# the value is arbitrary text delimited by newline. +# continuation, if needed, will be via the \ at the end of a line +# comments are indicated by a '#' as the first character. +# the keywords are case-INSENSITIVE +owner: Ron Minnich +email: rminnich@lanl.gov +#status: One of unsupported, unstable, stable +status: stable +explanation: +flash-types: sst28sf040 and similar +payload-types: etherboot +# e.g. linux, plan 9, wince, etc. +OS-types: Linux +# e.g. "Plan 9 interrupts don't work on this chipset" +OS-issues: +console-types: serial +# vga is unsupported, unstable, or stable +vga: +# Last-known-good follows the internationl date standard: day/month/year +last-known-good: 01/06/2002 +Comments: Can't use CONFIG_COMPRESS +Links: +Mainboard-revision: +# What other mainboards are like this one? List them here. +AKA: diff --git a/src/mainboard/asus/tx97le/config.etherboot b/src/mainboard/asus/tx97le/config.etherboot new file mode 100644 index 0000000000..fc2c21ab9a --- /dev/null +++ b/src/mainboard/asus/tx97le/config.etherboot @@ -0,0 +1,27 @@ +# Sample config file for Intel 430TX chipset on the Smartcore P5 + +# This will make a target directory of ./smartcore-p5 +target smartcore-p5 + +# ASUS CUA main board +mainboard digitallogic/smartcore-p5 + +# option HAVE_PIRQ_TABLE=1 +# Enable Serial Console for debugging +option SERIAL_CONSOLE=1 +option NO_KEYBOARD=1 +#nooption NO_KEYBOARD +#keyboard pc80 +option INBUF_COPY +option DEFAULT_CONSOLE_LOGLEVEL=7 +#option MAXIMUM_CONSOLE_LOGLEVEL=10 +#option DEBUG=1 +option USE_GENERIC_ROM=1 +option ROM_SIZE=262144 + + +# MEMORY TESTING USING MEMTEST +option USE_ELF_BOOT=1 + +payload ../eepro100.ebi +nooption RAMTEST diff --git a/src/mainboard/asus/tx97le/config.example b/src/mainboard/asus/tx97le/config.example new file mode 100644 index 0000000000..665bad9abc --- /dev/null +++ b/src/mainboard/asus/tx97le/config.example @@ -0,0 +1,29 @@ +# Sample config file for Intel 430TX chipset on the Smartcore P5 + +# This will make a target directory of ./smartcore-p5 +target smartcore-p5 + +# ASUS CUA main board +mainboard digitallogic/smartcore-p5 + +# option HAVE_PIRQ_TABLE=1 +# Enable Serial Console for debugging +option SERIAL_CONSOLE=1 +option NO_KEYBOARD +option INBUF_COPY +option DEFAULT_CONSOLE_LOGLEVEL=9 +option DEBUG +option USE_GENERIC_ROM=1 + +# MEMORY TESTING USING MEMTEST +option USE_ELF_BOOT=1 + +# *****************MODIFIED BY BHARATH******************** +# Path to your kernel (vmlinux) +linux /users/bxmx/kernels/vmlinux-2.4.14 + +# Kernel command line parameters +# *******************MODIFIED BY BHARATH **************** +commandline root=/dev/hdc2 console=ttyS0,115200 floppy=nodma single + +option RAMTEST diff --git a/src/mainboard/asus/tx97le/do_ramtest.inc b/src/mainboard/asus/tx97le/do_ramtest.inc new file mode 100644 index 0000000000..e22381e142 --- /dev/null +++ b/src/mainboard/asus/tx97le/do_ramtest.inc @@ -0,0 +1,5 @@ + mov $0x00000000, %eax + mov $0x0009ffff, %ebx + mov $16, %ecx + + CALLSP(ramtest) diff --git a/src/mainboard/asus/tx97le/irq_tables.c b/src/mainboard/asus/tx97le/irq_tables.c new file mode 100644 index 0000000000..2e33a2cc21 --- /dev/null +++ b/src/mainboard/asus/tx97le/irq_tables.c @@ -0,0 +1,42 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*18, /* there can be total 18 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x38, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x8a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0x80, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0, 0}, + {0,0x48, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x1, 0}, + {0,0x50, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x2, 0}, + {0,0x58, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x3, 0}, + {0,0x60, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x4, 0}, + {0,0x38, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0, 0}, + {0,0xa0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x88, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x98, {{0x61, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x90, {{0x60, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x78, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0, 0}, + {0x1,0x48, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x1, 0}, + {0x1,0x50, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x2, 0}, + {0x1,0x58, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x3, 0}, + {0x1,0x60, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x4, 0}, + {0x1,0x68, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x5, 0}, + {0x1,0x70, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x6, 0}, + {0x1,0x78, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x7, 0}, + } +}; diff --git a/src/mainboard/asus/tx97le/mainboard.c b/src/mainboard/asus/tx97le/mainboard.c new file mode 100644 index 0000000000..2d393d97a0 --- /dev/null +++ b/src/mainboard/asus/tx97le/mainboard.c @@ -0,0 +1,183 @@ +#include +#include + +#include + +// this needs to be moved about a bit to northbridge.c etc. + + +void mainboard_fixup() +{ + struct pci_dev *pm_pcidev; + // struct pci_dev *host_bridge_pcidev; + struct pci_dev *nic_pcidev; + unsigned smbus_io, pm_io; + unsigned int i, j; + printk_debug("intel_mainboard_fixup()\n"); + +#if 1 + pm_pcidev = pci_find_device(0x8086, 0x7113, 0); + nic_pcidev = pci_find_device(0x8086, 0x1229, 0); + // host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); +#endif +#if 1 + pci_write_config_byte(nic_pcidev, 0x3c, 21); +#endif +#if 0 + { + u8 byte; + u16 word; + u32 dword; + for(i = 0; i < 8; i++) { + pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); + printk_debug("DRB[i] = 0x%02x\n", byte); + } + pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); + printk_debug("DRAMC = 0x%02x\n", byte); + pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); + printk_debug("RPS = 0x%02x\n", byte); + pci_read_config_word(host_bridge_pcidev, 0x78, &word); + printk_debug("PGPOL = 0x%04x\n", word); + pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); + printk_debug("NBXCFG = 0x%04x\n", dword); + } + +#endif +#if 0 + + printk_debug("Reset Control Register\n"); + outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); + + printk_debug("port 92\n"); + outb((inb(0x92) & 0xFE), 0x92); + + printk_debug("Disable Nmi\n"); + outb(0, 0x70); + + printk_debug("enabling smbus\n"); +#if 0 + smbus_io = NewPciIo(0x10); +#else + smbus_io = 0xFFF0; +#endif + pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */ + pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ + + + printk_debug("enable pm functions\n"); +#if 0 + pm_io = NewPciIo(0x40); +#else + pm_io = 0xFF80; +#endif + pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ + + printk_debug("disabling smi\n"); + /* GLBEN */ + outw(0x00, pm_io + 0x20); + /* GLBCTL */ + outl((1 << 24), pm_io + 0x28); + + printk_debug("Disable more pm stuff\n"); + /* PMEN */ + outw((1 << 8), pm_io + 0x02); + /* PMCNTRL */ + outw((0x5 << 10) , pm_io + 0x4); + /* PMTMR */ + outl(0, pm_io + 0x08); + /* GPEN */ + outw(0, pm_io + 0x0e); + /* PCNTRL */ + outl(0, pm_io + 0x10); + /* GLBSTS */ + /* DEVSTS */ + /* GLBEN see above */ + /* GLBCTL see above */ + /* DEVCTL */ + outl(0, pm_io + 0x2c); + /* GPIREG */ + /* GPOREG */ + + printk_debug("Set the subsystem vendor id\n"); + pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); + + printk_debug("Disabling pm stuff in pci config space\n"); + +#define MAX_COUNTERS +#ifndef MAX_COUNTERS + /* counters to 0 */ +#define WHICH_COUNTERS(min,max) min +#else + /* max out the counters */ +#define WHICH_COUNTERS(min,max) max +#endif + + /* CNTA */ + pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF)); + + /* CNTB */ + pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df)); + + /* GPICTL */ + pci_write_config_dword(pm_pcidev, 0x4c, 0); + + /* DEVRESD */ + pci_write_config_dword(pm_pcidev, 0x50, 0); + + /* DEVACTA */ + pci_write_config_dword(pm_pcidev, 0x54, 0); + + /* DEVACTB */ + pci_write_config_dword(pm_pcidev, 0x58, 0); + + /* DEVRESA */ + pci_write_config_dword(pm_pcidev, 0x5c, 0); + + /* DEVRESB */ + pci_write_config_dword(pm_pcidev, 0x60, 0); + + /* DEVRESC */ + pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */ + + /* DEVRESE */ + pci_write_config_dword(pm_pcidev, 0x68, 0); + + /* DEVRESF */ + pci_write_config_dword(pm_pcidev, 0x6c, 0); + + /* DEVRESG */ + pci_write_config_dword(pm_pcidev, 0x70, 0); + + /* DEVRESH */ + pci_write_config_dword(pm_pcidev, 0x74, 0); + + /* DEVRESI */ + pci_write_config_dword(pm_pcidev, 0x78, 0); + + /* DEVRESJ */ + pci_write_config_dword(pm_pcidev, 0x7c, 0); + +#endif + +#if 1 + + /* Verify that smi is disabled */ + printk_debug("Testing SMI\r\n"); + { + u32 value; + pci_read_config_dword(pm_pcidev, 0x58, &value); + pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); + } + outb(inb(0xb2), 0xb2); + printk_debug("SMI disabled\r\n"); +#endif +#if 0 + + for(i = 0; i < 255; i++) { + printk_debug("%08x\r\n", i); + __rdtsc_delay2(1000000000UL, pm_io); + } +#endif +}