From 039f21b5e36d1010ff4c61def737556ce31714ca Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Wed, 25 Feb 2026 10:44:17 -0800 Subject: [PATCH] soc/intel/alderlake: Use common GSPI devfn mapping Replace platform-specific gspi.c with the common GSPI device function mapping implementation. Changes: - Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig - Define SOC_GSPI_DEVFN(n) macro in pci_devs.h - Remove platform-specific gspi.c file Change-Id: Ia1b2c3d4e5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/91314 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/Makefile.mk | 1 - src/soc/intel/alderlake/gspi.c | 25 ------------------- .../intel/alderlake/include/soc/pci_devs.h | 1 + 4 files changed, 2 insertions(+), 26 deletions(-) delete mode 100644 src/soc/intel/alderlake/gspi.c diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c78a09076d..4ab0b1c820 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -85,6 +85,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FEATURE + select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN select SOC_INTEL_COMMON_FEATURE_UART_DEVICES select SOC_INTEL_COMMON_FSP_RESET diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 2e97718bc2..35f84a5cb4 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo # all (bootblock, verstage, romstage, postcar, ramstage) -all-y += gspi.c all-y += pmutil.c all-y += spi.c diff --git a/src/soc/intel/alderlake/gspi.c b/src/soc/intel/alderlake/gspi.c deleted file mode 100644 index dd07b07f1a..0000000000 --- a/src/soc/intel/alderlake/gspi.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * This file is created based on Intel Alder Lake Processor PCH Datasheet - * Document number: 621483 - * Chapter number: 11 - */ - -#include -#include - -int gspi_soc_bus_to_devfn(unsigned int gspi_bus) -{ - switch (gspi_bus) { - case 0: - return PCH_DEVFN_GSPI0; - case 1: - return PCH_DEVFN_GSPI1; - case 2: - return PCH_DEVFN_GSPI2; - case 3: - return PCH_DEVFN_GSPI3; - } - return -1; -} diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 13cea6d2fc..15ec661870 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -282,6 +282,7 @@ #define PCI_DEVFN_UART0 PCH_DEVFN_UART0 #define PCI_DEVFN_UART1 PCH_DEVFN_UART1 #define PCI_DEVFN_UART2 PCH_DEVFN_UART2 +#define SOC_GSPI_DEVFN(n) PCH_DEVFN_GSPI##n #endif