erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

src/soc: Capitalize CPU, ACPI, RAM and ROM

Browse source 
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-07-29 18:31:16 +02:00 • committed by Martin Roth
commit 038e7247dc
41 changed files with 54 additions and 54 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/nvidia/tegra124/bootblock.c
View file

@ -34,7 +34,7 @@ static void run_next_stage(void *entry)
power_enable_and_ungate_cpu();
/* Repair ram on cluster0 and cluster1 after CPU is powered on. */
/* Repair RAM on cluster0 and cluster1 after CPU is powered on. */
ram_repair();
clock_cpu0_remove_reset();

2
src/soc/nvidia/tegra124/bootblock_asm.S
View file

@ -28,7 +28,7 @@
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

4
src/soc/nvidia/tegra124/include/soc/sdram_param.h
View file

@ -791,9 +791,9 @@ struct sdram_params {
uint32_t EmcCaTrainingTimingCntl2;
/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t SwizzleRankByteEncode;
/* Specifies enable and offset for patched boot rom write */
/* Specifies enable and offset for patched boot ROM write */
uint32_t BootRomPatchControl;
/* Specifies data for patched boot rom write */
/* Specifies data for patched boot ROM write */
uint32_t BootRomPatchData;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t McMtsCarveoutBom;

2
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
View file

@ -612,7 +612,7 @@ void lp0_resume(void)
power_on_main_cpu();
// Perform ram repair after cpu is powered on.
// Perform RAM repair after CPU is powered on.
ram_repair();
clear_cpu_resets();

2
src/soc/nvidia/tegra124/maincpu.S
View file

@ -32,7 +32,7 @@
.arm
ENTRY(maincpu_setup)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

2
src/soc/nvidia/tegra132/bootblock_asm.S
View file

@ -30,7 +30,7 @@
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

4
src/soc/nvidia/tegra132/ccplex.c
View file

@ -133,14 +133,14 @@ static void request_ram_repair(void)
stopwatch_init(&sw);
/* Perform cluster 0 ram repair */
/* Perform cluster 0 RAM repair */
reg = read32(&flow->ram_repair);
reg |= req;
write32(&flow->ram_repair, reg);
while ((read32(&flow->ram_repair) & sts) != sts)
;
/* Perform cluster 1 ram repair */
/* Perform cluster 1 RAM repair */
reg = read32(&flow->ram_repair_cluster1);
reg |= req;
write32(&flow->ram_repair_cluster1, reg);

2
src/soc/nvidia/tegra132/clock.c
View file

@ -508,7 +508,7 @@ void clock_cpu0_config(void)
/* wait and try again */
if (timeout >= CLK_SWITCH_TIMEOUT_US) {
printk(BIOS_ERR, "%s: PLLX programming timeout. "
"Switching cpu clock has falied.\n",
"Switching CPU clock has falied.\n",
__func__);
break;
}

4
src/soc/nvidia/tegra132/include/soc/sdram_param.h
View file

@ -794,9 +794,9 @@ struct sdram_params {
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t SwizzleRankByteEncode;
/* Specifies enable and offset for patched boot rom write */
/* Specifies enable and offset for patched boot ROM write */
uint32_t BootRomPatchControl;
/* Specifies data for patched boot rom write */
/* Specifies data for patched boot ROM write */
uint32_t BootRomPatchData;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t McMtsCarveoutBom;

2
src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
View file

@ -645,7 +645,7 @@ void lp0_resume(void)
power_on_main_cpu();
// Perform ram repair after cpu is powered on.
// Perform RAM repair after CPU is powered on.
ram_repair();
clear_cpu_resets();

2
src/soc/nvidia/tegra132/romstage.c
View file

@ -72,7 +72,7 @@ void romstage(void)
cbmem_initialize_empty();
ccplex_cpu_prepare();
printk(BIOS_INFO, "T132 romstage: cpu prepare done\n");
printk(BIOS_INFO, "T132 romstage: CPU prepare done\n");
ccplex_load_mts();
printk(BIOS_INFO, "T132 romstage: MTS loading done\n");

2
src/soc/nvidia/tegra210/bootblock_asm.S
View file

@ -30,7 +30,7 @@
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.

2
src/soc/nvidia/tegra210/ccplex.c
View file

@ -72,7 +72,7 @@ static void request_ram_repair(void)
stopwatch_init(&sw);
/* Perform ram repair */
/* Perform RAM repair */
reg = read32(&flow->ram_repair);
reg |= req;
write32(&flow->ram_repair, reg);

4
src/soc/nvidia/tegra210/include/soc/sdram_param.h
View file

@ -951,9 +951,9 @@ struct sdram_params {
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t SwizzleRankByteEncode;
/* Specifies enable and offset for patched boot rom write */
/* Specifies enable and offset for patched boot ROM write */
uint32_t BootRomPatchControl;
/* Specifies data for patched boot rom write */
/* Specifies data for patched boot ROM write */
uint32_t BootRomPatchData;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */

2
src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
View file

@ -1024,7 +1024,7 @@ void lp0_resume(void)
* 1 : MAX77621
*/
if (read32(pmc_scratch201_ptr) & PMIC_77621)
/* Set cpu rail 0.85V */
/* Set CPU rail 0.85V */
i2c_send(MAX77621_I2C_ADDR, MAX77621_VOUT_DATA);
else
/* Enable GPIO5 on MAX77620 PMIC */

2
src/soc/nvidia/tegra210/romstage.c
View file

@ -79,7 +79,7 @@ void romstage(void)
cbmem_initialize_empty();
ccplex_cpu_prepare();
printk(BIOS_INFO, "T210 romstage: cpu prepare done\n");
printk(BIOS_INFO, "T210 romstage: CPU prepare done\n");
romstage_mainboard_init();