From 02d5cb7fb23164cbd8ea77f48430a96f4f36fcc7 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 1 Nov 2000 03:54:54 +0000 Subject: [PATCH] adding support for L440GX. L440BX is next. --- src/mainboard/intel/l440gx/crt0.S | 26 ++--- src/mainboard/intel/l440gx/mainboard.c | 4 +- src/sdram/generic_sdram.inc | 114 +++++++++++++++++++++ src/southbridge/intel/piix4e/southbridge.c | 24 +++++ 4 files changed, 154 insertions(+), 14 deletions(-) create mode 100644 src/sdram/generic_sdram.inc diff --git a/src/mainboard/intel/l440gx/crt0.S b/src/mainboard/intel/l440gx/crt0.S index 4f80dd3a14..dd3a58850c 100644 --- a/src/mainboard/intel/l440gx/crt0.S +++ b/src/mainboard/intel/l440gx/crt0.S @@ -3,11 +3,10 @@ * */ -#include -#include - -#include "intel_conf.h" +#include +#include +#include /* * This is the entry code (the mkrom(8) utility makes a jumpvector * to this adddess. @@ -23,29 +22,29 @@ .text .code16 -#include "intel_start32.S" +#include -#include "NSC_SuperIO.S" +#include -#include "serial.S" +#include TTYS0_TX_STRING($ttyS0_test) /* initialize the RAM */ /* different for each motherboard */ -#include "intel_440ram-2.S" -#include "intel_ram.S" +#include +#include + #undef RAMTEST -#include "ramtest.S" +#ifdef RAMTEST +#include -#if 0 +#include movl $0x00000000, %eax movl $0x0009ffff, %ebx movl $24,%ecx CALLSP(ramtest) -#endif - #if 0 movl $0x08000000, %eax movl $0x08001000, %ebx @@ -57,6 +56,7 @@ movl $24,%ecx CALLSP(ramtest) #endif +#endif /* * Copy data into RAM and clear the BSS. Since these segments diff --git a/src/mainboard/intel/l440gx/mainboard.c b/src/mainboard/intel/l440gx/mainboard.c index a835d16c19..63d63f08fb 100644 --- a/src/mainboard/intel/l440gx/mainboard.c +++ b/src/mainboard/intel/l440gx/mainboard.c @@ -1,10 +1,12 @@ #include #include +#include + // this needs to be moved about a bit to northbridge.c etc. -void intel_mainboard_fixup() +void mainboard_fixup() { struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; unsigned smbus_io, pm_io; diff --git a/src/sdram/generic_sdram.inc b/src/sdram/generic_sdram.inc new file mode 100644 index 0000000000..0f89c06ecc --- /dev/null +++ b/src/sdram/generic_sdram.inc @@ -0,0 +1,114 @@ +jmp ram_initialize + + /* Estimate that SLOW_DOWN_IO takes about 50&76us*/ + /* delay for 200us */ + +#define DO_DELAY \ + movl $4, %edi ; \ +1: SLOW_DOWN_IO ; \ + decl %edi ; \ + jnz 1b + + + +ram_1: .string "Ram1\r\n" +ram_2: .string "Ram2\r\n" +ram_3: .string "Ram3\r\n" +ram_4: .string "Ram4\r\n" +ram_5: .string "Ram5\r\n" +ram_6: .string "Ram6\r\n" +ram_7: .string "Ram7\r\n" +ram_8: .string "Ram8\r\n" +ram_9: .string "Ram9\r\n" +ram_10: .string "Ram10\r\n" +ram_11: .string "Ram11\r\n" +ram_12: .string "Ram12\r\n" +ram_13: .string "Ram13\r\n" +ram_14: .string "Ram14\r\n" +ram_15: .string "Ram15\r\n" +ram_16: .string "Ram16\r\n" +ram_17: .string "Ram17\r\n" +ram_18: .string "Ram18\r\n" +ram_19: .string "Ram19\r\n" +ram_20: .string "Ram20\r\n" +no_memory_str: .string "No memory!\r\n" + +no_memory: TTYS0_TX_STRING($no_memory_str) +1: hlt /* stick here.. */ + jmp 1b + +ram_initialize: + /* this sets up the dram. */ + + TTYS0_TX_STRING($ram_1) + + /* Now, set registers we can set once to reasonable values */ + + CALL_LABEL(ram_set_registers) + + TTYS0_TX_STRING($ram_2) + + /* Now set those things we can auto detect */ + CALL_LABEL(ram_set_spd_registers) + + TTYS0_TX_STRING($ram_3) + + +/* now the fun begins. + turn on the dram and wait a while (this from the intel book) + turn power on and set the nop bit too + */ + TTYS0_TX_STRING($ram_4) + /* SDRAMC */ + SET_RAM_COMMAND(RAM_COMMAND_NOP) + + DO_DELAY + + ASSERT_RAM_COMMAND() /* nop command */ + + /* Precharge all */ + SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE) + ASSERT_RAM_COMMAND() + + /* wait until the all banks idle state... */ + + TTYS0_TX_STRING($ram_5) + + /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ + + SET_RAM_COMMAND(RAM_COMMAND_CBR) + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + ASSERT_RAM_COMMAND() + + TTYS0_TX_STRING($ram_6) + + /* mode register set */ + SET_RAM_MODE_REGISTER + + /* MAx[14:0] lines, + * MAx[2:0 ] 010 == burst mode of 4 + * MAx[3:3 ] 1 == interleave wrap type + * MAx[4:4 ] == CAS# latency bit + * MAx[6:5 ] == 01 + * MAx[12:7] == 0 + */ + + TTYS0_TX_STRING($ram_7) + + /* normal operation */ + SET_RAM_COMMAND(RAM_COMMAND_NONE) + + TTYS0_TX_STRING($ram_8) + + + /* Finally enable refresh */ + /* DRAMC */ + ENABLE_REFRESH() + + TTYS0_TX_STRING($ram_9) diff --git a/src/southbridge/intel/piix4e/southbridge.c b/src/southbridge/intel/piix4e/southbridge.c index da97da2f02..9060d9af0d 100644 --- a/src/southbridge/intel/piix4e/southbridge.c +++ b/src/southbridge/intel/piix4e/southbridge.c @@ -6,3 +6,27 @@ void southbridge_fixup() { } + +void nvram_on() +{ + /*; now set up PIIX4e registers 4e and 4f for nvram access. + ; 4e will have value 0xc3, 4f will have value 2 + ; we are going to PIIX4 function 0; the PIIX4 is device 0x12. + ; bit coding is 0x80000000 + 0x9000 (dev 0x12) + 0x4c (x4 aligned) + ; plus 2 or 3 (e or f) + */ + /* well, this turns on the 1 MB, but we might as well enable APIC + * access too + */ + + struct pci_dev *pcidev; + + pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL); + if (pcidev) pci_write_config_word(pcidev, 0x4e, 0x03c3); + +} + +// Have to talk to Eric Beiderman about this ... +void keyboard_on() +{ +}