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soc/intel/meteorlake: Hook up Pch Sleep Assertion widths

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Hook up devicetree to the assertion width UPDs, in the same way
that Tiger Lake does - specifically, only setting the UPDs if a
non-default value is set via devicetree; otherwise, use the
FSP default value.

Change-Id: Ifd92ef8217055eb7b558bc494a6586b35403c368
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86754
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-03-06 13:52:52 +00:00 • committed by Matt DeVillier
commit 02ca72b2d4
2 changed files with 68 additions and 0 deletions
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49
src/soc/intel/meteorlake/chip.h
View file

@ -457,6 +457,55 @@ struct soc_intel_meteorlake_config {
*/
bool cpu_replacement_check;
enum {
SLP_S3_ASSERTION_DEFAULT,
SLP_S3_ASSERTION_60_US,
SLP_S3_ASSERTION_1_MS,
SLP_S3_ASSERTION_50_MS,
SLP_S3_ASSERTION_2_S,
} pch_slp_s3_min_assertion_width;
enum {
SLP_S4_ASSERTION_DEFAULT,
SLP_S4_ASSERTION_1S,
SLP_S4_ASSERTION_2S,
SLP_S4_ASSERTION_3S,
SLP_S4_ASSERTION_4S,
} pch_slp_s4_min_assertion_width;
enum {
SLP_SUS_ASSERTION_DEFAULT,
SLP_SUS_ASSERTION_0_MS,
SLP_SUS_ASSERTION_500_MS,
SLP_SUS_ASSERTION_1_S,
SLP_SUS_ASSERTION_4_S,
} pch_slp_sus_min_assertion_width;
enum {
SLP_A_ASSERTION_DEFAULT,
SLP_A_ASSERTION_0_MS,
SLP_A_ASSERTION_4_S,
SLP_A_ASSERTION_98_MS,
SLP_A_ASSERTION_2_S,
} pch_slp_a_min_assertion_width;
/*
* PCH PM Reset Power Cycle Duration
* NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
* stretch duration programmed in the following registers:
* - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
* - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
* - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
*/
enum {
POWER_CYCLE_DURATION_DEFAULT,
POWER_CYCLE_DURATION_1S,
POWER_CYCLE_DURATION_2S,
POWER_CYCLE_DURATION_3S,
POWER_CYCLE_DURATION_4S,
} pch_reset_power_cycle_duration;
/* ISA Serial Base selection. */
enum {
ISA_SERIAL_BASE_ADDR_3F8,

19
src/soc/intel/meteorlake/fsp_params.c
View file

@ -22,6 +22,7 @@
#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
@ -658,6 +659,24 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
/* Enable the energy efficient turbo mode */
s_cfg->EnergyEfficientTurbo = 1;
s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
/* Apply minimum assertion width settings if non-zero */
if (config->pch_slp_s3_min_assertion_width)
s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width;
if (config->pch_slp_s4_min_assertion_width)
s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width;
if (config->pch_slp_sus_min_assertion_width)
s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width;
if (config->pch_slp_a_min_assertion_width)
s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width;
/* Set Power Cycle Duration */
if (config->pch_reset_power_cycle_duration)
s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->pch_slp_s4_min_assertion_width,
config->pch_slp_s3_min_assertion_width,
config->pch_slp_a_min_assertion_width,
config->pch_reset_power_cycle_duration);
/* Un-Demotion from Demoted C1 need to be disable when
* C1 auto demotion is disabled */
s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;