diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/cezanne/memmap.c
+++ b/src/soc/amd/cezanne/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/glinda/memmap.c
+++ b/src/soc/amd/glinda/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/mendocino/memmap.c
+++ b/src/soc/amd/mendocino/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c
index 1b45b9c93c..063c100bc9 100644
--- a/src/soc/amd/phoenix/memmap.c
+++ b/src/soc/amd/phoenix/memmap.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -66,6 +68,9 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	if (CONFIG(PLATFORM_USES_FSP2_0))
 		read_fsp_resources(dev, idx);
 	else
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 2bbf28589a..bdbfb426e5 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }