erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Revert "samsung/exynos5: add resource functions for the display port"

Browse source 
This reverts commit 9427ca151e

Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things.
coreboot memory table:
 0. 0000000050000000-000000005000ffff: RESERVED
 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
 2. 0000014004000000-00000140044007ff: RESERVED

Before this patch:
coreboot memory table:
 0. 0000000040000000-00000000bfefffff: RAM
 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES

Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec
Reviewed-on: http://review.coreboot.org/2914
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-03-26 04:25:46 +01:00
commit 0175587c5e
7 changed files with 143 additions and 102 deletions
Download patch file Download diff file Expand all files Collapse all files

38
src/mainboard/google/snow/devicetree.cb
View file

@ -17,18 +17,30 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# FIXME: this is just a stub for now
chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
register "bpp" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
register "lower_margin" = "3"
register "vsync" = "5"
register "left_margin" = "80"
register "right_margin" = "48"
register "hsync" = "32"
register "lcdbase" = "0x50000000"
device cpu_cluster 0 on
end
device domain 0 on
chip drivers/generic/generic # I2C0 controller
device i2c 6 on end # ?
device i2c 9 on end # ?
end
chip cpu/samsung/exynos5-common/displayport
register "xres" = "1366"
register "yres" = "768"
register "bpp" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
register "lower_margin" = "3"
register "vsync" = "5"
register "left_margin" = "80"
register "right_margin" = "48"
register "hsync" = "32"
register "lcdbase" = "0x10000000"
end
end
end