From 010cfa28421bd52f1f16798ddf5b2116ea3f7f7a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 7 Apr 2025 23:22:34 +0200 Subject: [PATCH] doc/internals/devicetree_language: multiple segment groups supported coreboot supports more than just one PCI segment group by having more than one domain in the devicetree, so update the PCI device description. Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206 Reviewed-by: Felix Singer Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Maximilian Brune --- Documentation/internals/devicetree_language.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md index ab1b646c29..43a22337d0 100644 --- a/Documentation/internals/devicetree_language.md +++ b/Documentation/internals/devicetree_language.md @@ -973,11 +973,11 @@ The pci device type defines a PCI or PCIe device on the PCI logical bus. Resources for all PCI devices are assigned automatically, or must be assigned in code if they're non-standard. -Currently, only a single segment is supported, but there is work to make -multiple different segments supported, each with a bus 0. Because the -bus is not specified, It's assumed that all pci devices that are not -behind a pci bridge device are on bus 0. If there are additional pci -busses in a chip, they can be added behind their bridge device. +Only a single segment group is supported per domain, but there can be multiple +domains to support the case of multiple segment groups, each with a bus 0. +Because the bus is not specified, It's assumed that all pci devices that are +not behind a pci bridge device are on bus 0. If there are additional pci busses +in a chip, they can be added behind their bridge device. Examples: