From 00c3255214c9c339c9ab41e9d4a3feac05dfa851 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 26 Dec 2024 13:59:32 -0800 Subject: [PATCH] soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 21. The previous offset of 0x10, inherited from Meteor Lake code, caused an issue that resulted in: - Temporary deactivation of Thunderbolt PCI devices during ramstage - Failure to generate critical ACPI SSDT power management data for the port This error led to instability in PCIe tunneling during power state transitions. Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/pcie_rp.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 1b302fda0e..604e7af1b2 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -5,13 +5,15 @@ #include /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) - */ + * Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" + * specifies that the first Thunderbolt PCIe root port number is 21. TBT's LCAP registers return + * port index which starts from 21 (usually for other PCIe root ports index starts from + * 1). Thus, keeping lcap_port_base 21 for TBT, so that coreboot's PCIe remapping logic can + * return a correct index (0-based). +*/ static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 21 }, { 0 } };