diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c
index 1b302fda0e..604e7af1b2 100644
--- a/src/soc/intel/pantherlake/pcie_rp.c
+++ b/src/soc/intel/pantherlake/pcie_rp.c
@@ -5,13 +5,15 @@
 #include <soc/pcie.h>
 
 /*
- * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
- * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
- * PCIe remapping logic can return correct index (0-based)
- */
+ * Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID"
+ * specifies that the first Thunderbolt PCIe root port number is 21. TBT's LCAP registers return
+ * port index which starts from 21 (usually for other PCIe root ports index starts from
+ * 1). Thus, keeping lcap_port_base 21 for TBT, so that coreboot's PCIe remapping logic can
+ * return a correct index (0-based).
+*/
 
 static const struct pcie_rp_group tbt_rp_groups[] = {
-	{ .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
+	{ .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 21 },
 	{ 0 }
 };