From 00b994f9de737d71c421e1b3dbfa4f54736ea8c2 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Mon, 5 Oct 2015 19:49:51 -0700 Subject: [PATCH] veyron_rialto: Initial import into firmware branch This is a straight copy of src/mainboard/google/veyron_rialto from ToT. The next patch in the series will show differences necessary to get it to build in the firmware branch. The reason for doing it this way is because a lot of changes from ToT have already been applied to other non-laptop Veyron boards. So it doesn't make a whole lot of sense to re-apply them individually just for Rialto. And since Rialto has been in the tree for a long time and has accumulated a lot of history, things would be quite broken up until the later patches if we tried. Coreboot for Rialto will not compile with this. The follow-up patch must be applied for it to build successfully. CQ-DEPEND=CL:304108 BUG=chrome-os-partner:46150 BRANCH=firmware-veyron TEST=built and booted on Rialto w/ follow-up patch Change-Id: I90eb9af3b4f31b656ecdded20e0a556fef2609d0 Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/304107 Reviewed-by: Alexandru Stan --- src/mainboard/google/veyron_rialto/Kconfig | 72 ++++++++++ .../google/veyron_rialto/Kconfig.name | 2 + .../google/veyron_rialto/Makefile.inc | 42 ++++++ src/mainboard/google/veyron_rialto/board.h | 30 +++++ src/mainboard/google/veyron_rialto/boardid.c | 49 +++++++ .../google/veyron_rialto/bootblock.c | 78 +++++++++++ src/mainboard/google/veyron_rialto/chromeos.c | 113 ++++++++++++++++ .../google/veyron_rialto/devicetree.cb | 26 ++++ .../google/veyron_rialto/mainboard.c | 127 ++++++++++++++++++ .../google/veyron_rialto/memlayout.ld | 1 + src/mainboard/google/veyron_rialto/reset.c | 31 +++++ src/mainboard/google/veyron_rialto/romstage.c | 116 ++++++++++++++++ .../google/veyron_rialto/sdram_configs.c | 54 ++++++++ .../sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc | 77 +++++++++++ .../veyron_rialto/sdram_inf/sdram-unused.inc | 3 + 15 files changed, 821 insertions(+) create mode 100644 src/mainboard/google/veyron_rialto/Kconfig create mode 100644 src/mainboard/google/veyron_rialto/Kconfig.name create mode 100644 src/mainboard/google/veyron_rialto/Makefile.inc create mode 100644 src/mainboard/google/veyron_rialto/board.h create mode 100644 src/mainboard/google/veyron_rialto/boardid.c create mode 100644 src/mainboard/google/veyron_rialto/bootblock.c create mode 100644 src/mainboard/google/veyron_rialto/chromeos.c create mode 100644 src/mainboard/google/veyron_rialto/devicetree.cb create mode 100644 src/mainboard/google/veyron_rialto/mainboard.c create mode 100644 src/mainboard/google/veyron_rialto/memlayout.ld create mode 100644 src/mainboard/google/veyron_rialto/reset.c create mode 100644 src/mainboard/google/veyron_rialto/romstage.c create mode 100644 src/mainboard/google/veyron_rialto/sdram_configs.c create mode 100644 src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc create mode 100644 src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig new file mode 100644 index 0000000000..0061bfadc9 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -0,0 +1,72 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +if BOARD_GOOGLE_VEYRON_RIALTO + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_4096 + select CHROMEOS_VBNV_FLASH + select COMMON_CBFS_SPI_WRAPPER + select HAVE_HARD_RESET + select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH + select RAM_CODE_SUPPORT + select SOC_ROCKCHIP_RK3288 + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/veyron_rialto + +config MAINBOARD_PART_NUMBER + string + default "Veyron_Rialto" + +config MAINBOARD_VENDOR + string + default "Google" + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0xFF690000 + +config PMIC_BUS + int + default 0 + +endif # BOARD_GOOGLE_VEYRON_RIALTO diff --git a/src/mainboard/google/veyron_rialto/Kconfig.name b/src/mainboard/google/veyron_rialto/Kconfig.name new file mode 100644 index 0000000000..80d805223a --- /dev/null +++ b/src/mainboard/google/veyron_rialto/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_VEYRON_RIALTO + bool "Veyron_Rialto" diff --git a/src/mainboard/google/veyron_rialto/Makefile.inc b/src/mainboard/google/veyron_rialto/Makefile.inc new file mode 100644 index 0000000000..ea1c6063e7 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += sdram_configs.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_rialto/board.h b/src/mainboard/google/veyron_rialto/board.h new file mode 100644 index 0000000000..5fd45dba53 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H + +#include +#include + +#define GPIO_RESET GPIO(0, B, 5) + +void setup_chromeos_gpios(void); + +#endif /* __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H */ diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c new file mode 100644 index 0000000000..f7cddcc4fe --- /dev/null +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include + +uint8_t board_id(void) +{ + static int id = -1; + static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ + + if (id < 0) { + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "Board ID: %d.\n", id); + } + + return id; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c new file mode 100644 index 0000000000..e87d8d17e2 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +void bootblock_mainboard_early_init() +{ + if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); + } + +} + +void bootblock_mainboard_init(void) +{ + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + + /* Turn on all leds */ + gpio_output(GPIO(7, A, 0), 1); /* LED_READY */ + gpio_output(GPIO(7, B, 5), 1); /* Ready2_LED */ + gpio_output(GPIO(7, B, 3), 1); /* LED_SYNCING */ + gpio_output(GPIO(7, B, 7), 1); /* LED_ERROR */ + + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ + i2c_init(CONFIG_PMIC_BUS, 400*KHz); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rkclk_configure_cpu(APLL_1416_MHZ); + + /* i2c1 for tpm */ + write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); + i2c_init(1, 400*KHz); + + /* spi2 for firmware ROM */ + write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); + write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c new file mode 100644 index 0000000000..267c9359bc --- /dev/null +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include +#include + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY_SERVO GPIO(0, B, 1) +#define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1) +#define GPIO_DEVELOPER_SWITCH GPIO(7, B, 2) + + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY_SERVO); + gpio_input_pullup(GPIO_RECOVERY_PUSHKEY); + gpio_input(GPIO_DEVELOPER_SWITCH); // board has pull up/down resistor. +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_WP.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_WP); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + /* Note for early development, we want to support both servo and + * pushkey recovery buttons in firmware boot stages. + */ + gpios->gpios[count].port = GPIO_RECOVERY_PUSHKEY.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = !get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Power Button: GPIO active low */ + gpios->gpios[count].port = GPIO_POWER.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: GPIO active high */ + gpios->gpios[count].port = GPIO_DEVELOPER_SWITCH.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Reset: GPIO active high (output) */ + gpios->gpios[count].port = GPIO_RESET.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "reset", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + // GPIO_DEVELOPER_SWITCH is active high. + return gpio_get(GPIO_DEVELOPER_SWITCH); +} + +int get_recovery_mode_switch(void) +{ + // Both RECOVERY_SERVO and RECOVERY_PUSHKEY are low active. + return !(gpio_get(GPIO_RECOVERY_SERVO) && + gpio_get(GPIO_RECOVERY_PUSHKEY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} diff --git a/src/mainboard/google/veyron_rialto/devicetree.cb b/src/mainboard/google/veyron_rialto/devicetree.cb new file mode 100644 index 0000000000..c40bbbbc4e --- /dev/null +++ b/src/mainboard/google/veyron_rialto/devicetree.cb @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_NONE" + register "framebuffer_bits_per_pixel" = "16" +end diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c new file mode 100644 index 0000000000..35de7e0508 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +static void configure_usb(void) +{ + gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */ +} + +static void configure_emmc(void) +{ + write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA); + write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN); + write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD); + + gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ +} + +static void configure_codec(void) +{ + write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */ + i2c_init(2, 400*KHz); /* CODEC I2C */ + + write32(&rk3288_grf->iomux_i2s, IOMUX_I2S); + write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK); + + rk808_configure_ldo(6, 1800); /* VCC18_CODEC */ + + /* AUDIO IO domain 1.8V voltage selection */ + write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6)); + rkclk_configure_i2s(12288000); +} + +static void configure_3g(void) +{ + /* Force 3G modem off to avoid confusing the EHCI host and + * causing problems during enumeration/init */ + gpio_output(GPIO(5, C, 1), 1); /* 3G_SHUTDOWN */ + gpio_output(GPIO(4, D, 2), 0); /* 3G_ON_OFF */ +} + +static void mainboard_init(device_t dev) +{ + gpio_output(GPIO_RESET, 0); + + configure_usb(); + configure_emmc(); + configure_codec(); + configure_3g(); + /* No video. */ + + elog_init(); + elog_add_watchdog_reset(); + elog_add_boot_reason(); + + /* If recovery mode is detected, reduce frequency and voltage to reduce + * heat in case machine is left unattended. chrome-os-partner:41201. */ + if (recovery_mode_enabled()) { + printk(BIOS_DEBUG, "Reducing APLL freq for recovery mode.\n"); + rkclk_configure_cpu(APLL_600_MHZ); + rk808_configure_buck(1, 900); + } +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} + +void mainboard_power_on_backlight(void) +{ + return; +} diff --git a/src/mainboard/google/veyron_rialto/memlayout.ld b/src/mainboard/google/veyron_rialto/memlayout.ld new file mode 100644 index 0000000000..ead7f47838 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/memlayout.ld @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c new file mode 100644 index 0000000000..f35860844f --- /dev/null +++ b/src/mainboard/google/veyron_rialto/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include + +#include "board.h" + +void hard_reset(void) +{ + gpio_output(GPIO_RESET, 1); + while (1) + ; +} diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c new file mode 100644 index 0000000000..e845a4228b --- /dev/null +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +static void regulate_vdd_log(unsigned int mv) +{ + unsigned int duty_ns; + const u32 period_ns = 2000; /* pwm period: 2000ns */ + const u32 max_regulator_mv = 1350; /* 1.35V */ + const u32 min_regulator_mv = 870; /* 0.87V */ + + write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1); + + assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); + + duty_ns = (max_regulator_mv - mv) * period_ns / + (max_regulator_mv - min_regulator_mv); + + pwm_init(1, period_ns, duty_ns); +} + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + +static void sdmmc_power_off(void) +{ + rk808_configure_ldo(4, 0); /* VCCIO_SD */ + rk808_configure_ldo(5, 0); /* VCC33_SD */ +} + +void main(void) +{ + timestamp_add_now(TS_START_ROMSTAGE); + + console_init(); + configure_l2ctlr(); + tsadc_init(); + + /* Need to power cycle SD card to ensure it is properly reset. */ + sdmmc_power_off(); + + /* vdd_log 1200mv is enough for ddr run 666Mhz */ + regulate_vdd_log(1200); + + timestamp_add_now(TS_BEFORE_INITRAM); + + sdram_init(get_sdram_config()); + + timestamp_add_now(TS_AFTER_INITRAM); + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + sdram_size_mb(), DCACHE_WRITEBACK); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); + + cbmem_initialize_empty(); + + run_ramstage(); +} diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c new file mode 100644 index 0000000000..3213ff7a7f --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +static struct rk3288_sdram_params sdram_configs[] = { +#include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */ +}; + +const struct rk3288_sdram_params *get_sdram_config() +{ + u32 ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) + || sdram_configs[ramcode].dramtype == UNUSED) + die("Invalid RAMCODE."); + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc new file mode 100644 index 0000000000..9afd04fdd1 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc new file mode 100644 index 0000000000..06498f7f14 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc @@ -0,0 +1,3 @@ +{ + .dramtype= UNUSED +}, \ No newline at end of file