From 00b4a61dc53c68b47d1452c387409f2eadf32c93 Mon Sep 17 00:00:00 2001 From: Naresh Solanki Date: Wed, 27 Nov 2024 01:41:40 +0530 Subject: [PATCH] soc/amd/glinda/cpu: Update smbios parameters Update smbios parameters for cache type, operation mode & error correction type. source: UEFI reference BIOS Change-Id: If8eaa54c9a0086f4d397a7ddb01009acfd3f1aee Signed-off-by: Naresh Solanki Reviewed-on: https://review.coreboot.org/c/coreboot/+/85637 Reviewed-by: Maximilian Brune Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index 26380077f2..680b0957d3 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -17,6 +17,22 @@ unsigned int smbios_processor_external_clock(void) { return 100; // 100 MHz } + +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST; +} + static void zen_2_3_init(struct device *dev) { check_mca();